1141 search results - page 226 / 229 » Compiler-Directed Performance Model Construction for Paralle... |
112
Voted
ISCA
2006
IEEE
15 years 10 days ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
113
click to vote
ESWA
2007
15 years 9 days ago
2007
The credit card industry has been growing rapidly recently, and thus huge numbers of consumers’ credit data are collected by the credit department of the bank. The credit scorin...
150
click to vote
OOPSLA
2010
Springer
14 years 10 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
106
click to vote
HPCA
2005
IEEE
16 years 22 days ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
104
click to vote
RECOMB
2005
Springer
16 years 20 days ago
2005
Springer
Abstract. In order to guarantee that the optimal motif is found, traditional pattern-driven approaches perform an exhaustive search over all candidate motifs of length l. We develo...