Sciweavers

244 search results - page 33 / 49
» Compiler-Optimized Simulation of Large-Scale Applications on...
Sort
View
CASES
2007
ACM
15 years 7 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...
130
Voted
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 10 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
FGCS
2007
125views more  FGCS 2007»
15 years 3 months ago
An autonomic tool for building self-organizing Grid-enabled applications
In this paper we present CAMELotGrid, a tool to manage Grid computations of Cellular Automata that support the efficient simulation of complex systems modeled by a very large numb...
Gianluigi Folino, Giandomenico Spezzano
CODES
2008
IEEE
15 years 5 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
CASES
2008
ACM
15 years 5 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano