105 search results - page 15 / 21 » Compiler-managed partitioned data caches for low power |
105
Voted
EUROSYS
2007
ACM
15 years 8 months ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
102
Voted
IOPADS
1996
15 years 28 days ago
1996
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
PLDI
2005
ACM
15 years 5 months ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
140
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CAL
2008
14 years 11 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
113
Voted
TVLSI
2008
14 years 11 months ago
2008
The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...