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149
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MICRO
2003
IEEE
95views Hardware» more  MICRO 2003»
15 years 11 months ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded appl...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke
147
Voted
DATE
2002
IEEE
130views Hardware» more  DATE 2002»
15 years 11 months ago
Assigning Program and Data Objects to Scratchpad for Energy Reduction
The number of embedded systems is increasing and a remarkable percentage is designed as mobile applications. For the latter, the energy consumption is a limiting factor because of...
Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter M...
MTDT
1999
IEEE
68views Hardware» more  MTDT 1999»
15 years 10 months ago
Unbalanced Cache Systems
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...
David L. Rhodes, Wayne Wolf
ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 10 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
CASES
2007
ACM
15 years 10 months ago
Non-transparent debugging for software-pipelined loops
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
Hugo Venturini, Frédéric Riss, Jean-...