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DATE
2009
IEEE
189views Hardware» more  DATE 2009»
16 years 1 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
CF
2009
ACM
16 years 23 days ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
CASES
2006
ACM
16 years 6 days ago
Adaptive object code compression
Previous object code compression schemes have employed static and semiadaptive compression algorithms to reduce the size of instruction memory in embedded systems. The suggestion ...
John Gilbert, David M. Abrahamson
LCPC
2005
Springer
15 years 11 months ago
Manipulating MAXLIVE for Spill-Free Register Allocation
Abstract. Many embedded systems use single-chip microcontrollers which have no on-chip RAM. In such a system, the processor registers must hold all live data values. Nanocontroller...
Shashi Deepa Arcot, Henry G. Dietz, Sarojini Priya...
IEEEPACT
2002
IEEE
15 years 11 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany