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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 8 months ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
IWMM
2000
Springer
137views Hardware» more  IWMM 2000»
15 years 8 months ago
Cycles to Recycle: Garbage Collection on the IA-64
The IA-64, Intel's 64-bit instruction set architecture, exhibits a number of interesting architectural features. Here we consider those features as they relate to supporting ...
Richard L. Hudson, J. Eliot B. Moss, Sreenivas Sub...
AIPS
2007
15 years 7 months ago
Evaluating Temporal Planning Domains
The last eight years have seen dramatic progress in temporal planning as highlighted by the temporal track in the last three International Planning Competitions (IPC). However, ou...
William Cushing, Daniel S. Weld, Subbarao Kambhamp...
CC
2008
Springer
123views System Software» more  CC 2008»
15 years 6 months ago
Automatic Transformation of Bit-Level C Code to Support Multiple Equivalent Data Layouts
Portable low-level C programs must often support multiple equivalent in-memory layouts of data, due to the byte or bit order of the compiler, architecture, or external data formats...
Marius Nita, Dan Grossman
DAC
2005
ACM
15 years 6 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim