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CJ
2006
84views more  CJ 2006»
13 years 6 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ICS
2001
Tsinghua U.
13 years 10 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
ICFP
2008
ACM
14 years 6 months ago
Space profiling for parallel functional programs
This paper presents a semantic space profiler for parallel functional programs. Building on previous work in sequential profiling, our tools help programmers to relate runtime res...
Daniel Spoonhower, Guy E. Blelloch, Robert Harper,...
ICPPW
2009
IEEE
14 years 1 months ago
Comparing and Optimising Parallel Haskell Implementations for Multicore Machines
—In this paper, we investigate the differences and tradeoffs imposed by two parallel Haskell dialects running on multicore machines. GpH and Eden are both constructed using the h...
Jost Berthold, Simon Marlow, Kevin Hammond, Abdall...
CACM
2010
179views more  CACM 2010»
13 years 6 months ago
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating syste...
Peter Sewell, Susmit Sarkar, Scott Owens, Francesc...