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119
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JRTIP
2008
249views more  JRTIP 2008»
15 years 2 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
161
Voted
IPPS
2005
IEEE
15 years 8 months ago
A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
153
Voted
CDES
2006
184views Hardware» more  CDES 2006»
15 years 4 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
105
Voted
ASAP
2002
IEEE
78views Hardware» more  ASAP 2002»
15 years 7 months ago
Optical Network Reconfiguration for Signal Processing Applications
Roger D. Chamberlain, Mark A. Franklin, Praveen Kr...
119
Voted
ARC
2010
Springer
138views Hardware» more  ARC 2010»
15 years 6 months ago
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel app...
Esam El-Araby, Vikram K. Narayana, Tarek A. El-Gha...