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» Compiling SA-C Programs to FPGAs: Performance Results
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MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
15 years 4 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
IEEEPACT
2009
IEEE
15 years 6 months ago
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
Tipp Moseley, Dirk Grunwald, Ramesh Peri
IPPS
2009
IEEE
15 years 6 months ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...
IMS
2000
125views Hardware» more  IMS 2000»
15 years 3 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
PPPJ
2009
ACM
15 years 6 months ago
Phase detection using trace compilation
Dynamic compilers can optimize application code specifically for observed code behavior. Such behavior does not have to be stable across the entire program execution to be bene...
Christian Wimmer, Marcelo Silva Cintra, Michael Be...