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» Compiling SA-C Programs to FPGAs: Performance Results
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91
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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
13 years 5 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
TACO
2008
130views more  TACO 2008»
14 years 9 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
80
Voted
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 2 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
IPPS
2003
IEEE
15 years 2 months ago
Performing DNA Comparison on a Bio-Inspired Tissue of FPGAs
String comparison is a critical issue in many application domains, including speech recognition, contents search, and bioinformatics. The similarity between two strings of lengths...
Matteo Canella, Filippo Miglioli, Alessandro Bogli...
DATE
2010
IEEE
166views Hardware» more  DATE 2010»
15 years 2 months ago
A special-purpose compiler for look-up table and code generation for function evaluation
Abstract—Elementary functions are extensively used in computer graphics, signal and image processing, and communication systems. This paper presents a special-purpose compiler th...
Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, S...