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» Compiling SA-C Programs to FPGAs: Performance Results
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93
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LCTRTS
2007
Springer
15 years 5 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
CGO
2009
IEEE
15 years 3 months ago
Communication-Sensitive Static Dataflow for Parallel Message Passing Applications
Message passing is a very popular style of parallel programming, used in a wide variety of applications and supported by many APIs, such as BSD sockets, MPI and PVM. Its importance...
Greg Bronevetsky
99
Voted
ICS
2005
Tsinghua U.
15 years 5 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
VEE
2005
ACM
143views Virtualization» more  VEE 2005»
15 years 5 months ago
Virtual machine showdown: stack versus registers
Virtual machines (VMs) are commonly used to distribute programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the desi...
Yunhe Shi, David Gregg, Andrew Beatty, M. Anton Er...
91
Voted
CASES
2001
ACM
15 years 3 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen