Sciweavers

500 search results - page 94 / 100
» Compiling SA-C Programs to FPGAs: Performance Results
Sort
View
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
15 years 3 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
PPOPP
2010
ACM
15 years 9 months ago
Lazy binary-splitting: a run-time adaptive work-stealing scheduler
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...
Alexandros Tzannes, George C. Caragea, Rajeev Baru...
CISIS
2010
IEEE
15 years 6 months ago
Threaded Dynamic Memory Management in Many-Core Processors
—Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may ...
Edward C. Herrmann, Philip A. Wilsey
HASKELL
2006
ACM
15 years 5 months ago
Statically typed linear algebra in Haskell
Many numerical algorithms are specified in terms of operations on vectors and matrices. Matrix operations can be executed extremely efficiently using specialized linear algebra k...
Frederik Eaton
130
Voted
JSW
2008
101views more  JSW 2008»
14 years 11 months ago
Graphical Mission Specification and Partitioning for Unmanned Underwater Vehicles
- The use of Unmanned Underwater Vehicles (UUVs) has been proposed for several different types of applications including hydrographic surveys (e.g., mapping the ocean floor and exp...
Gary Giger, Mahmut T. Kandemir, John Dzielski