82 search results - page 11 / 17 » Compiling code accelerators for FPGAs |
CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
102
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TCAD
2008
14 years 11 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
146
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FCCM
2011
IEEE
14 years 3 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
TVLSI
2008
14 years 11 months ago
2008
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...