82 search results - page 12 / 17 » Compiling code accelerators for FPGAs |
86
Voted
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
FPL
2009
Springer
15 years 4 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
ASAP
2005
IEEE
15 years 5 months ago
2005
IEEE
The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application a...
119
Voted
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
118
click to vote
CL
2008
Springer
14 years 11 months ago
2008
Springer
One of the most promising approaches to Java acceleration in embedded systems is a bytecode-to-C ahead-of-time compiler (AOTC). It improves the performance of a Java virtual machi...