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» Compiling code accelerators for FPGAs
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77
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FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
15 years 3 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
DATE
2009
IEEE
144views Hardware» more  DATE 2009»
15 years 4 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
15 years 3 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
15 years 6 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
71
Voted
CGO
2007
IEEE
15 years 3 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke