82 search results - page 5 / 17 » Compiling code accelerators for FPGAs |
TVLSI
2008
14 years 11 months ago
2008
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
TACO
2008
14 years 11 months ago
2008
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
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ICDE
2011
IEEE
14 years 3 months ago
2011
IEEE
—The rapidly increasing amount of data available for real-time analysis (i.e., so-called operational business intelligence) is creating an interesting opportunity for creative ap...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Elementary functions are extensively used in computer graphics, signal and image processing, and communication systems. This paper presents a special-purpose compiler th...
FPL
2006
Springer
15 years 3 months ago
2006
Springer
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...