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» Compiling code accelerators for FPGAs
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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 8 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
CASES
2006
ACM
15 years 5 months ago
Syntax-driven implementation of software programming language control constructs and expressions on FPGAs
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...
Neil C. Audsley, Michael Ward
FPL
2004
Springer
205views Hardware» more  FPL 2004»
15 years 5 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
ASPLOS
2006
ACM
15 years 5 months ago
Accelerator: using data parallelism to program GPUs for general-purpose uses
GPUs are difficult to program for general-purpose uses. Programmers can either learn graphics APIs and convert their applications to use graphics pipeline operations or they can ...
David Tarditi, Sidd Puri, Jose Oglesby
DAC
2004
ACM
15 years 5 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh