Sciweavers

1133 search results - page 14 / 227
» Compiling for Speculative Architectures
Sort
View
79
Voted
CF
2005
ACM
15 years 1 months ago
On the energy-efficiency of speculative hardware
Microprocessor trends are moving towards wider architectures and more aggressive speculation. With the increasing transistor budgets, energy consumption has become a critical desi...
Nana B. Sam, Martin Burtscher
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
15 years 6 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...
HPCA
1998
IEEE
15 years 4 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
MICRO
1998
IEEE
92views Hardware» more  MICRO 1998»
15 years 4 months ago
Predictive Techniques for Aggressive Load Speculation
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
Glenn Reinman, Brad Calder
EUROMICRO
1998
IEEE
15 years 4 months ago
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
Joan-Manuel Parcerisa, Antonio González