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IJPP
2000
94views more  IJPP 2000»
15 years 4 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
PVLDB
2008
134views more  PVLDB 2008»
15 years 4 months ago
Evita raced: metacompilation for declarative networks
Declarative languages have recently been proposed for many new applications outside of traditional data management. Since these are relatively early research efforts, it is import...
Tyson Condie, David Chu, Joseph M. Hellerstein, Pe...
SAMOS
2010
Springer
15 years 3 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
CC
2010
Springer
179views System Software» more  CC 2010»
15 years 11 months ago
Validating Register Allocation and Spilling
Abstract. Following the translation validation approach to highassurance compilation, we describe a new algorithm for validating a posteriori the results of a run of register alloc...
Silvain Rideau, Xavier Leroy
138
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AICCSA
2007
IEEE
89views Hardware» more  AICCSA 2007»
15 years 11 months ago
Software/Configware Implementation of Combinatorial Algorithms
This paper discusses an approach for solving combinatorial problems by combining software and dynamically reconfigurable hardware (configware). The suggested technique avoids inst...
Iouliia Skliarova, Valery Sklyarov