931 search results - page 104 / 187 » Compiling for vector-thread architectures |
144
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DAC
1997
ACM
15 years 9 months ago
1997
ACM
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
140
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DAC
1994
ACM
15 years 8 months ago
1994
ACM
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
121
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DAC
1992
ACM
15 years 8 months ago
1992
ACM
This paper describes a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant ...
143
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DATE
2004
IEEE
15 years 8 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
149
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ICECCS
1995
IEEE
15 years 8 months ago
1995
IEEE
Achieving fault-tolerance using a primary-backup approach involves overhead of recovery such as activating the backup and propagating execution states, which may a ect the timelin...