931 search results - page 24 / 187 » Compiling for vector-thread architectures |
77
Voted
SIGPLAN
2008
14 years 9 months ago
2008
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
93
Voted
DATE
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
118
Voted
ESOP
1992
Springer
15 years 1 months ago
1992
Springer
We have designed, implemented, and proved the correctness of a compiler generator that accepts action semantic descriptions of imperative programming languages. The generated comp...
TCAD
2008
14 years 9 months ago
2008
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
SAMOS
2004
Springer
15 years 2 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...