Sciweavers

931 search results - page 75 / 187
» Compiling for vector-thread architectures
Sort
View
144
Voted
ASPLOS
1998
ACM
15 years 8 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
CASES
2006
ACM
15 years 10 months ago
Syntax-driven implementation of software programming language control constructs and expressions on FPGAs
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...
Neil C. Audsley, Michael Ward
126
Voted
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
15 years 9 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
125
Voted
ASPLOS
1991
ACM
15 years 8 months ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
VEE
2005
ACM
143views Virtualization» more  VEE 2005»
15 years 10 months ago
Optimized interval splitting in a linear scan register allocator
We present an optimized implementation of the linear scan register allocation algorithm for Sun Microsystems’ Java HotSpotTM client compiler. Linear scan register allocation is ...
Christian Wimmer, Hanspeter Mössenböck