Sciweavers

931 search results - page 84 / 187
» Compiling for vector-thread architectures
Sort
View
ICPP
2007
IEEE
15 years 11 months ago
Loop-level Speculative Parallelism in Embedded Applications
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In...
Md. Mafijul Islam, Alexander Busck, Mikael Engbom,...
ICSM
2006
IEEE
15 years 10 months ago
Source-Level Linkage: Adding Semantic Information to C++ Fact-bases
Facts extracted from source code have been used to support a variety of software engineering activities, ranging from architectural understanding, through detection of design patt...
Daqing Hou, H. James Hoover
ISCAS
2006
IEEE
116views Hardware» more  ISCAS 2006»
15 years 10 months ago
Neural network stream processing core (NnSP) for embedded systems
Abstract— NnSP is a stream-based programmable and codelevel statically reconfigurable processor for realization of neural networks in embedded systems. NnSP is provided with a n...
Hadi Esmaeilzadeh, Pooya Saeedi, Babak Nadjar Araa...
EGH
2005
Springer
15 years 10 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
ERLANG
2004
ACM
15 years 10 months ago
HiPE on AMD64
Erlang is a concurrent functional language designed for developing large-scale, distributed, fault-tolerant systems. The primary implementation of the language is the Erlang/OTP s...
Daniel Luna, Mikael Pettersson, Konstantinos F. Sa...