931 search results - page 8 / 187 » Compiling for vector-thread architectures |
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
64
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CF
2004
ACM
15 years 2 months ago
2004
ACM
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information dir...
102
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PPOPP
2003
ACM
15 years 2 months ago
2003
ACM
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
CASES
2005
ACM
14 years 11 months ago
2005
ACM
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...