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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 7 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
MAM
2007
157views more  MAM 2007»
15 years 3 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
151
Voted
JPDC
2000
141views more  JPDC 2000»
15 years 3 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...

Publication
502views
17 years 3 months ago
Spatio-Temporal Histograms
This paper presents a framework for building and continuously maintaining spatio-temporal histograms (ST-Histograms, for short). ST-Histograms are used for selectivity estimation o...
Hicham G. Elmongui, Mohamed F. Mokbel, Walid G. Ar...
ICFEM
2009
Springer
15 years 10 months ago
Qualitative Action Systems
An extension to action systems is presented facilitating the modeling of continuous behavior in the discrete domain. The original action system formalism has been developed by Back...
Bernhard K. Aichernig, Harald Brandl, Willibald Kr...