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VMV
2004
80views Visualization» more  VMV 2004»
15 years 1 months ago
Reducing State Changes with a Pipeline Buffer
A limiting factor in the performance of a rendering system is the number of state changes, i.e., changes of the attributes material, texture, shader program, etc., in the stream o...
Jens Krokowski, Harald Räcke, Christian Sohle...
98
Voted
WWW
2004
ACM
16 years 10 days ago
Web engineering with the visual software circuit board
The Visual Software Circuit Board (VSCB) platform supports a component based development methodology towards the development of software systems. The circuit board design techniqu...
Hovhannes Avoyan, Barry Levine
AGENTS
2000
Springer
15 years 4 months ago
Dataflow plan execution for software agents
Recent research has made it possible to build information agents that retrieve and integrate information from the World Wide Web. Although there now exist solutions for modeling W...
Greg Barish, Dan DiPasquo, Craig A. Knoblock, Stev...
DAC
1994
ACM
15 years 3 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
15 years 8 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...