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EMSOFT
2007
Springer
15 years 9 months ago
A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation
In networked control systems the controller of a physicallydistributed plant is implemented as a collection of tightlyinteracting, concurrent processes running on a distributed ex...
Alessandro Pinto, Luca P. Carloni, Alberto L. Sang...
105
Voted
ISPASS
2006
IEEE
15 years 9 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
156
Voted
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 9 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
114
Voted
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 9 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
94
Voted
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 10 months ago
Estimating functional coverage in bounded model checking
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
Daniel Große, Ulrich Kühne, Rolf Drechs...