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110
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GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
134
Voted
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 8 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
130
Voted
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
15 years 7 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
ICANN
2005
Springer
15 years 9 months ago
Interpolation Mechanism of Functional Networks
In this paper, the interpolation mechanism of functional networks is discussed. A kind of fourlayer (with 1 input and 1 output unit) and a five-layer (with double input and single...
Yong-Quan Zhou, Licheng Jiao
136
Voted
FLOPS
2010
Springer
15 years 2 months ago
Proving Injectivity of Functions via Program Inversion in Term Rewriting
Injectivity is one of the important properties for functions while it is undecidable in general and decidable for linear treeless functions. In this paper, we show new sufficient c...
Naoki Nishida, Masahiko Sakai