2607 search results - page 193 / 522 » Complete Functional Synthesis |
152
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ICCAD
2004
IEEE
16 years 29 days ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
129
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ICPR
2010
IEEE
15 years 11 months ago
2010
IEEE
We propose a learning method for gait synthesis from a sequence of shapes(frames) with the ability to extrapolate to novel data. It involves the application of PCA, first to redu...
119
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
143
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FCCM
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
137
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level o...