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138
Voted
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
14 years 4 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
187
Voted
ECCV
1998
Springer
16 years 6 months ago
From Reference Frames to Reference Planes: Multi-View Parallax Geometry and Applications
Abstract. This paper presents a new framework for analyzing the geometry of multiple 3D scene points from multiple uncalibrated images, based on decomposing the projection of these...
Michal Irani, P. Anandan, Daphna Weinshall
174
Voted
AVSS
2009
IEEE
15 years 11 months ago
A 3D Face Model for Pose and Illumination Invariant Face Recognition
Generative 3D face models are a powerful tool in computer vision. They provide pose and illumination invariance by modeling the space of 3D faces and the imaging process. The powe...
Pascal Paysan, Reinhard Knothe, Brian Amberg, Sami...
154
Voted
CODES
2008
IEEE
15 years 11 months ago
Distributed flit-buffer flow control for networks-on-chip
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
Nicola Concer, Michele Petracca, Luca P. Carloni
143
Voted
CODES
2007
IEEE
15 years 11 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...