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KDD
2012
ACM
201views Data Mining» more  KDD 2012»
13 years 6 months ago
Low rank modeling of signed networks
Trust networks, where people leave trust and distrust feedback, are becoming increasingly common. These networks may be regarded as signed graphs, where a positive edge weight cap...
Cho-Jui Hsieh, Kai-Yang Chiang, Inderjit S. Dhillo...
DAC
2006
ACM
16 years 5 months ago
Optimality study of resource binding with multi-Vdds
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 4 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
POPL
2010
ACM
16 years 1 months ago
A Relational Modal Logic for Higher-Order Stateful ADTs
The method of logical relations is a classic technique for proving the equivalence of higher-order programs that implement the same observable behavior but employ different intern...
Derek Dreyer, Georg Neis, Andreas Rossberg, Lars B...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 28 days ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson