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DATE
2010
IEEE
175views Hardware» more  DATE 2010»
15 years 1 months ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
15 years 6 months ago
Test-model based hierarchical DFT synthesis
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Curre...
Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, ...
FOIS
2006
14 years 11 months ago
Linking the Gene Ontology with Social Ontology: A Prolegomena to the Ontology of Personhood
The Gene Ontology captures information at a very small scale, namely: molecular function, biological process, and cellular components. At this level, the Gene Ontology project shou...
David R. Koepsell
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 1 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
109
Voted
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
15 years 6 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah