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111
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
120
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...
129
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
114
Voted
ASAP
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
112
Voted
ITC
2000
IEEE
15 years 8 months ago
2000
IEEE
We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse duplex systems in t...