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» Completeness and Performance Of The APO Algorithm
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DAC
2005
ACM
15 years 11 months ago
Multilevel full-chip routing for the X-based architecture
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-J...
ICS
2010
Tsinghua U.
15 years 7 months ago
Cache Replacement Policies for Multicore Processors
Almost all of the modern computers use multiple cores, and the number of cores is expected to increase as hardware prices go down, and Moore's law fails to hold. Most of the ...
Avinatan Hassidim
FPGA
2004
ACM
120views FPGA» more  FPGA 2004»
15 years 3 months ago
Flexibility measurement of domain-specific reconfigurable hardware
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
Katherine Compton, Scott Hauck
ASPDAC
2005
ACM
120views Hardware» more  ASPDAC 2005»
14 years 12 months ago
STACCATO: disjoint support decompositions from BDDs through symbolic kernels
Abstract— A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component...
Stephen Plaza, Valeria Bertacco
JFR
2006
109views more  JFR 2006»
14 years 10 months ago
Alice: An information-rich autonomous vehicle for high-speed desert navigation
This paper describes the implementation and testing of Alice, the California Institute of Technology's entry in the 2005 DARPA Grand Challenge. Alice utilizes a highly networ...
Lars B. Cremean, Tully B. Foote, Jeremy H. Gillula...