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» Completing high-quality global routes
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FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
15 years 1 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 3 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
SIGCOMM
2004
ACM
15 years 2 months ago
Routing in a delay tolerant network
We formulate the delay-tolerant networking routing problem, where messages are to be moved end-to-end across a connectivity graph that is time-varying but whose dynamics may be kn...
Sushant Jain, Kevin R. Fall, Rabin K. Patra
ICCAD
2008
IEEE
110views Hardware» more  ICCAD 2008»
15 years 6 months ago
NTHU-Route 2.0: a fast and stable global router
—We present in this paper a fast and stable global router called NTHU-Route 2.0 that improves the solution quality and runtime of a state-of-the-art router, NTHU-Route, by the fo...
Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang
DAC
2007
ACM
15 years 10 months ago
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang