412 search results - page 39 / 83 » Completion for Multiple Reduction Orderings |
DSD
2007
IEEE
15 years 5 months ago
2007
IEEE
The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) ...
107
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ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
104
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WIOPT
2010
IEEE
14 years 9 months ago
2010
IEEE
—The downlink performance of cellular networks is known to be strongly limited by inter-cell interference. In order to mitigate this interference, a number of frequency reuse sch...
91
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CVPR
2005
IEEE
16 years 1 months ago
2005
IEEE
In this paper, we present a novel approach to solving the supervised dimensionality reduction problem by encoding an image object as a general tensor of 2nd or higher order. First...
CHES
2007
Springer
15 years 5 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...