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» Complexity Analysis of H.264 Decoder for FPGA Design
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253
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TCAD
2011
14 years 10 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
134
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FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 15 days ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
15 years 10 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter
115
Voted
ICIP
2007
IEEE
15 years 10 months ago
Rate-Distortion Analysis and Bit Allocation Strategy for Motion Estimation at the Decoder using Maximum Likelihood Technique in
Numerous approaches for distributed video coding have been recently proposed. One of main motivations for these techniques is the possibility of achieving complexity tradeoffs bet...
Ivy H. Tseng, Antonio Ortega
132
Voted
IPPS
2002
IEEE
15 years 8 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...