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ICCAD
2006
IEEE
95views Hardware» more  ICCAD 2006»
16 years 3 months ago
Timing model reduction for hierarchical timing analysis
— In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, ea...
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, ...
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
16 years 3 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
16 years 3 months ago
Multigrid-Like Technique for Power Grid Analysis
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
ICDE
2010
IEEE
194views Database» more  ICDE 2010»
16 years 1 months ago
Visualizing cost-based XQuery optimization
Abstract— Developing a full-fledged cost-based XQuery optimizer is a fairly complex task. Nowadays, there is little knowledge concerning suitable cost formulae and optimization ...
Andreas M. Weiner, Theo Härder, Renato Olivei...
HICSS
2009
IEEE
177views Biometrics» more  HICSS 2009»
16 years 1 months ago
Intelligent Alarm Processing: From Data Intensive to Information Rich
The requirement for power system operators to respond more efficiently to the stressed power system conditions that may create large number of alarms asks fort advanced alarm proc...
Mladen Kezunovic, Yufan Guan