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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 11 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
NOMS
2008
IEEE
181views Communications» more  NOMS 2008»
15 years 11 months ago
Coordinated management of power usage and runtime performance
— With the continued growth of computing power and reduction in physical size of enterprise servers, the need for actively managing electrical power usage in large datacenters is...
Malgorzata Steinder, Ian Whalley, James E. Hanson,...
PDP
2008
IEEE
15 years 11 months ago
Routing Performance in a Hierarchical DHT-based Overlay Network
The scalability properties of DHT based overlay networks is considered satisfactory. However, in large scale systems this might still cause a problem since they have a logarithmic...
Isaías Martinez-Yelmo, Rubén Cuevas ...
RTSS
2008
IEEE
15 years 11 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
15 years 11 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...