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IPPS
2006
IEEE
15 years 10 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
IPPS
2006
IEEE
15 years 10 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
IPPS
2006
IEEE
15 years 10 months ago
QoS-based management of multiple shared resource in dynamic real-time systems
Dynamic real-time systems require adaptive resource management to accommodate varying processing needs. We address the problem of resource management with multiple shared resource...
Klaus H. Ecker, Frank Drews, Jens Lichtenberg
IPPS
2006
IEEE
15 years 10 months ago
Battery-aware router scheduling in wireless mesh networks
Wireless mesh networks recently emerge as a flexible, low-cost and multipurpose networking platform with wired infrastructure connected to the Internet. A critical issue in mesh ...
Chi Ma, Zhenghao Zhang, Yuanyuan Yang
IPPS
2006
IEEE
15 years 10 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
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