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145
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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 9 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
148
Voted
KBSE
2005
IEEE
15 years 9 months ago
Automating experimentation on distributed testbeds
Engineering distributed systems is a challenging activity. This is partly due to the intrinsic complexity of distributed systems, and partly due to the practical obstacles that de...
Yanyan Wang, Matthew J. Rutherford, Antonio Carzan...
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
15 years 9 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
JCDL
2005
ACM
152views Education» more  JCDL 2005»
15 years 9 months ago
In the company of readers: the digital library book as "practiced place"
Most digital libraries (DLs) necessarily focus on the complex issues that arise when library collections are freed from their physical anchors in buildings and on paper. Typical i...
Nancy Kaplan, Yoram Chisik
151
Voted
SBCCI
2005
ACM
98views VLSI» more  SBCCI 2005»
15 years 9 months ago
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
José Carlos S. Palma, César A. M. Ma...
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