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ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
15 years 10 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
15 years 10 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2005
IEEE
95views Hardware» more  ICCAD 2005»
15 years 10 months ago
Application-specific network-on-chip architecture customization via long-range link insertion
Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either complete...
Ümit Y. Ogras, Radu Marculescu
LATIN
2010
Springer
15 years 8 months ago
Compact Rich-Functional Binary Relation Representations
Binary relations are an important abstraction arising in a number of data representation problems. Each existing data structure specializes in the few basic operations required by ...
Jérémy Barbay, Francisco Claude, Gon...
DATE
2009
IEEE
107views Hardware» more  DATE 2009»
15 years 8 months ago
Learning early-stage platform dimensioning from late-stage timing verification
— Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/...
Kai Richter, Marek Jersak, Rolf Ernst