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» Complexity reduction of C-Algorithm
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VLSID
2007
IEEE
146views VLSI» more  VLSID 2007»
16 years 1 months ago
Architecting Microprocessor Components in 3D Design Space
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004,...
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 1 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
HPCA
2008
IEEE
16 years 1 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
POPL
2006
ACM
16 years 1 months ago
A hierarchical model of data locality
In POPL 2002, Petrank and Rawitz showed a universal result-finding optimal data placement is not only NP-hard but also impossible to approximate within a constant factor if P = NP...
Chengliang Zhang, Chen Ding, Mitsunori Ogihara, Yu...
SODA
2010
ACM
235views Algorithms» more  SODA 2010»
15 years 10 months ago
Algorithmic Lower Bounds for Problems Parameterized by Clique-width
Many NP-hard problems can be solved efficiently when the input is restricted to graphs of bounded tree-width or clique-width. In particular, by the celebrated result of Courcelle,...
Fedor V. Fomin, Petr A. Golovach, Daniel Lokshtano...