Sciweavers

271 search results - page 44 / 55
» Complexity-Effective Superscalar Processors
Sort
View
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
16 years 2 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
CGO
2008
IEEE
15 years 11 months ago
Branch-on-random
We propose a new instruction, branch-on-random, that is like a standard conditional branch, except rather than specifying the condition on which the branch should be taken, it spe...
Edward Lee, Craig B. Zilles
129
Voted
ISPASS
2007
IEEE
15 years 11 months ago
Last-Touch Correlated Data Streaming
Recent research advocates address-correlating predictors to identify cache block addresses for prefetch. Unfortunately, address-correlating predictors require correlation data sto...
Michael Ferdman, Babak Falsafi
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
15 years 10 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee
EUROPAR
2005
Springer
15 years 10 months ago
Non-uniform Instruction Scheduling
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
Joseph J. Sharkey, Dmitry V. Ponomarev