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JSA
2011
76views more  JSA 2011»
14 years 6 months ago
Transactional memories for multi-processor FPGA platforms
Christoforos Kachris, Chidamber Kulkarni
CGF
1999
70views more  CGF 1999»
14 years 11 months ago
Modelling and Rendering Graphics Scenes Composed of Multiple Volumetric Datasets
This paper presents a method for modelling graphics scenes consisting of multiple volumetric objects. A twolevel hierarchical representation is employed, which enables the reducti...
Adrian Leu, Min Chen
CASES
2009
ACM
15 years 3 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
15 years 3 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm