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123
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ISPD
1998
ACM
91views Hardware» more  ISPD 1998»
15 years 8 months ago
Estimation of maximum current envelope for power bus analysis and design
In this paper we present an input pattern independent method to compute the maximum current envelope, which is an upper bound over all possible current waveforms drawn by a circui...
Sudhakar Bobba, Ibrahim N. Hajj
144
Voted
ISSS
1997
IEEE
142views Hardware» more  ISSS 1997»
15 years 8 months ago
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination
- An approach for broadband modem FIR filter design optimization is presented. It addresses the minimization of the number of addersubtractors used in the hardware implementation o...
Robert Pasko, Patrick Schaumont, Veerle Derudder, ...
ICCAD
1996
IEEE
85views Hardware» more  ICCAD 1996»
15 years 7 months ago
Exploiting regularity for low-power design
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
Renu Mehra, Jan M. Rabaey
156
Voted
DAGM
2007
Springer
15 years 7 months ago
Greedy-Based Design of Sparse Two-Stage SVMs for Fast Classification
Cascades of classifiers constitute an important architecture for fast object detection. While boosting of simple (weak) classifiers provides an established framework, the design of...
Rezaul Karim, Martin Bergtholdt, Jörg H. Kapp...
102
Voted
FPL
2008
Springer
116views Hardware» more  FPL 2008»
15 years 5 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...