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UIST
1999
ACM
15 years 9 months ago
Supporting Awareness and Interaction Through Collaborative Virtual Interfaces
This paper explores interfaces to virtual environments supporting multiple users. An interface to an environment allowing interaction with virtual artefacts is constructed, drawin...
Mike Fraser, Steve Benford, Jon Hindmarsh, Christi...
116
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ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
15 years 8 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 8 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...
ASAP
1997
IEEE
155views Hardware» more  ASAP 1997»
15 years 8 months ago
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
15 years 6 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch