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» Compositional Memory Systems for Data Intensive Applications
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123
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CODES
2009
IEEE
15 years 7 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
105
Voted
HPCA
2008
IEEE
16 years 22 days ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
117
Voted
PPOPP
2010
ACM
15 years 7 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
98
Voted
WSNA
2003
ACM
15 years 5 months ago
Analyzing and modeling encryption overhead for sensor network nodes
Recent research in sensor networks has raised security issues for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in...
Prasanth Ganesan, Ramnath Venugopalan, Pushkin Ped...
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 5 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...