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MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
16 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
FAW
2007
Springer
110views Algorithms» more  FAW 2007»
16 years 1 months ago
Maximizing the Number of Independent Labels in the Plane
In this paper, we consider a map labeling problem to maximize the number of independent labels in the plane. We first investigate the point labeling model that each label can be ...
Kuen-Lin Yu, Chung-Shou Liao, Der-Tsai Lee
229
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HPDC
2006
IEEE
16 years 1 months ago
Scheduling Mixed Workloads in Multi-grids: The Grid Execution Hierarchy
Consider a workload in which massively parallel tasks that require large resource pools are interleaved with short tasks that require fast response but consume fewer resources. We...
Mark Silberstein, Dan Geiger, Assaf Schuster, Miro...
HPDC
2006
IEEE
16 years 1 months ago
Path Grammar Guided Trace Compression and Trace Approximation
Trace-driven simulation is an important technique used in the evaluation of computer architecture innovations. However using it for studying parallel computers and applications is...
Xiaofeng Gao, Allan Snavely, Larry Carter
INFOCOM
2006
IEEE
16 years 1 months ago
Flow Scheduling for End-Host Multihoming
Abstract— Fueled by the competing DSL and Cable technologies, residential broadband access has seen a significant spread in availability to the point that many users have a choi...
Nathanael Thompson, Guanghui He, Haiyun Luo
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