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ARITH
2007
IEEE
14 years 18 days ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
VIP
2001
13 years 7 months ago
High-speed Parameterisable Hough Transform Using Reconfigurable Hardware
Recent developments in reconfigurable hardware technologies have offered high-density high-speed devices with the ability for custom computing whilst maintaining the flexibility o...
Dixon D. S. Deng, Hossam A. ElGindy
ASAP
2004
IEEE
140views Hardware» more  ASAP 2004»
13 years 10 months ago
Decimal Floating-Point Division Using Newton-Raphson Iteration
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
Liang-Kai Wang, Michael J. Schulte
ARITH
2003
IEEE
13 years 11 months ago
High-Radix Iterative Algorithm for Powering Computation
A high-radix composite algorithm for the computation of the powering function (¤¦¥ ) is presented in this paper. The algorithm consists of a sequence of overlapped operations: ...
José-Alejandro Piñeiro, Milos D. Erc...
ARITH
2005
IEEE
13 years 8 months ago
Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization
This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both 2-D Discrete Cosine Transform and Inverse DCT. The architecture uses a...
Khan Wahid, Vassil S. Dimitrov, Graham A. Jullien